* (1) (2) (3) Enhancement mode: Vth = -2.0 to -4.0 V (VDS = -10 V, ID = -1 mA) Low leakage current: IDSS = -10 µA (max) (VDS = -100 V) 3. Packaging and Internal Circuit 1: Gate 2: Drain 3: Source TO-220SIS 4. Absolute Maximum Ratings (Note) (Ta = 25 unless otherwise specified) Characteristics D
TJ9A10M3 Datasheet (199.10 KB)
TJ9A10M3
Toshiba ↗ Semiconductor
199.10 KB
Mosfets.
TJ9A10M3
MOSFETs Silicon P-Channel MOS (U-MOS)
TJ9A10M3
1. Applications
* Switching Voltage Regulators Low drain-source on-resistance: RDS(O.
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