TC551001AFTL-70LT

SILICON GATE CMOS STATIC RAM

Toshiba

TC551001AFTL-70LT Features

* with an operating Current of 5mNMHz (typ.) and a minimum cycle time of 70ns. When CE1 is a logical high, or CE2 is low, the device is placed in a low power standby mode in which the standby current is 2~ typically. The TC551 001 APL has three control inputs. Chip enable inputs (CE1, CE2) allow for d

TC551001AFTL-70LT General Description

The TC551 001APL is a 1,048,576 bit CMOS static random access memory organized as 131,072 words by 8 bits and operated from a single 5V power supply. Advanced circuit techniques provide both high speed and low power features with an operating Current of 5mNMHz (typ.) and a minimum cycle time of 70n.

TC551001AFTL-70LT Datasheet (273.73 KB)