TC551001APL-70L - SILICON GATE CMOS STATIC RAM
TC551001APL-70L Features
* with an operating current of 5mAlMHz (typ.) and a minimum cycle time of 70ns. When CE1 is a logical high, or CE2 is low, the device is placed in a low power standby mode in which the standby current is 2~ typically. The TC551 001 APL has three control inputs. Chip enable inputs (CE1, CE2) allow for
