TQ1090 Datasheet - TriQuint Semiconductor

TQ1090 11-Output Configurable Clock Buffer

The core of the TQ1090 is a Phase-Locked Loop (PLL) that continuously compares the reference clock (REFCLK) to the feedback clock (FBIN), maintaining a zero frequency difference between the two. Since one of the outputs is always connected to FBIN, the PLL keeps the propagation delay between the out.

TQ1090 Features

* Q0 14 GND 15 Q1 Q2 16 17 MUX Divide Logic ÷2 Output Buffers Group C Group A Group B 1 GND 28 27 S1 S0 Q8 Q7 VDD 18 26 VDD

* Wide frequency range: 33 MHz to 45 MHz 65 MHz to 90 MHz and 130 MHz to 180 MHz

* Output configurations: four outputs at fREF four outputs at 2x fREF t

TQ1090 Datasheet (247.02 KB)