TA7S20, TA7S04 Datasheet - Triscend

TA7S20 Triscend A7S Configurable System-on-Chip Platform

! High-performance, 32-bit ARM7TDMI RISC Processor * Popular, industry-standard 32bit RISC processor * Binary and source code compatible with other ARM7/ARM7TDMI variants * Widespread C/C++ compiler, source-level debugger, and RTOS support * Superior code density usin.

www.DataSheet4U.com Triscend A7S Configurable System-on-Chip Platform ® August, 2002 (Version 1.10) ! Industry’s first complete 32-bit Configurable System-on-Chip (CSoC) High-performance, low-power consumption, 32-bit RISC processor (ARM7TDMI™) 8Kbyte mixed instruction/data cache 16Kbyte internal scratchpad RAM Next-generation embedded programmable logic architecture (up to 25,600 ASIC gates) High-performance dedicated internal bus (up to 455Mb.

TA7S20 Features

* , and hold timing. The CPU connects directly to external memory, eliminating any potential latency incurred by using the CSI bus. For low frequency or minimal applications, the ARM7TDMI processor directly fetches its instructions from external Flash. The A7S optionally supports external SDRAM, offer

TA7S04_Triscend.pdf