P2V28S40ATP-7 Datasheet, Sdram, Vanguard International Semiconductor

P2V28S40ATP-7 Features

• Sdram ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time (Min.) CL=2 CL=3 -7 7ns 45ns CL=2 CL=3 V28S20D 20ns 5.4ns 63ns 85mA 85mA 85mA 1mA P2V28S20/30/40ATP -75 -8 10ns 7.5ns 45ns 20ns 6ns 5

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P2V28S40ATP-7

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Vanguard International Semiconductor

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📄 Datasheet

Description:

128mb sdram. P2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and P2V28S30ATP is organized as 4-b

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P2V28S40ATP-7

Vanguard International Semiconductor

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