W5500 Datasheet - WIZnet

W5500 Hardwired TCP/IP embedded Ethernet controller

7 HOST Interface 11 2.1 SPI Operation Mode 13 2.2 SPI Frame14 2.2.1 Address Phase14 2.2.2 Control Phase 15 2.2.3 Data Phase 17 2.3 Variable Length Data Mode (VDM) 17 2.3.1 Write Access in VDM 18 2.3.2 Read Access in VDM 21 2.4 Fixed Length Data Mode (FDM) 24 2.4.1 Write Acce.

W5500 Datasheet Version 1.1.0 http://www.wiznet.co.kr © Copyright 2013 WIZnet Co., Ltd. All rights reserved. W5500 The W5500 chip is a Hardwired TCP/IP embedded Ethernet controller that provides easier Internet connection to embedded systems. W5500 enables users to have the Internet connectivity in their applications just by using the single chip in which TCP/IP stack, 10/100 Ethernet MAC and PHY embedded. WIZnet‘s Hardwired TCP/IP is the market-proven technology that supports TCP, UDP, IPv4, I.

W5500 Features

* - Supports Hardwired TCP/IP Protocols : TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE - Supports 8 independent sockets simultaneously - Supports Power down mode - Supports Wake on LAN over UDP - Supports High Speed Serial Peripheral Interface(SPI MODE 0, 3) - Internal 32Kbytes Memory for TX/RX Buffers - 10

W5500-WIZnet.pdf