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XC5210 - Field Programmable Gate Arrays

Download the XC5210 datasheet PDF. This datasheet also covers the XC5200 variant, as both devices belong to the same field programmable gate arrays family and are provided as variant models within a single manufacturer datasheet.

Features

  • Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”) - Price competitive with Gate Arrays.
  • System Level Features - System performance beyond 50 MHz - 6 levels of interconnect hierarchy - VersaRing™ I/O Interface for pin-locking - Dedicated carry logic for high-speed arithmetic functions - Cascade chain for wide input functions - Built-in IEEE 1149.1 JTAG bound.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (XC5200-Xilinx.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Xilinx (now AMD)

Part Number Description
XC5215 Field Programmable Gate Arrays
XC5200 Field Programmable Gate Arrays
XC5202 Field Programmable Gate Arrays
XC5204 Field Programmable Gate Arrays
XC5206 Field Programmable Gate Arrays

Full PDF Text Transcription

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Product Obsolete or Under Obsolescence 0 R XC5200 Series Field Programmable Gate Arrays November 5, 1998 (Version 5.2) 0 7* Product Specification Features • Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”) - Price competitive with Gate Arrays • System Level Features - System performance beyond 50 MHz - 6 levels of interconnect hierarchy - VersaRing™ I/O Interface for pin-locking - Dedicated carry logic for high-speed arithmetic functions - Cascade chain for wide input functions - Built-in IEEE 1149.
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