VP16256 Datasheet (Zarlink Semiconductor)

VP16256, Programmable FIR FIlter

VP16256 Programmable FIR FIlter Advance Information DS4548 ISSUE 4.0 August 1998 The VP16256 contains sixteen multiplier - accumulators, which can be multi cycled to provide from 16 to 128 stages of digital filtering.

Input data and coefficients are both represented by 16-bit two’s PIN 1 complement numbers with coefficients converted internally to 12 bits and the results being accumulated up to 32 bits.

In 16-tap mode the device samples data at the system clock rate of up to 40MHz.

If a lower s

VP16256 Features

* EPROM ADDR DATA CHANGE COEFF POWER-ON RESET RES I Sixteen MACs in a Single Device I Basic Mode is 16-Tap Filter at up to 40MHz I OUTPUT DATA INPUT DATA VP 16256 EPROM SCLK GND I I I I I Fig. 1 A dual filter application EPROM ADDR DATA CHANGE COEFF POWER-ON RESET RES COEFFICIENTS Sample Rates P