* 1
* 2 Single-Ended Input
* Selectable Capture Buffer Size
* PLL for Clock Multiplication
* Reference Ladder Top and Bottom Accessible
* Linear Power Scaling with Sample Rate
* FPGA Training Pattern
* AEC-Q100 Grade 2 Qualified
* Power-Do
ADC08B200Q Datasheet (960.53 KB)
ADC08B200Q
960.53 KB
8-bit a/d converter.
ADC08B200
www.ti.com
SNAS388F
* MARCH 2007
* REVISED APRIL 2013
ADC08B200 / ADC08B200Q 8-Bit, 200 MSPS A/D Converter with Capture B.
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