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CD54HC195 - 4-Bit Parallel Access Register

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CD54HC195 Product details

Description

Asynchronous Master Reset J, K, (D) Inputs to First Stage Fully Synchronous Serial or Parallel Data Transfer Shift Right and Parallel Load Capability Complementary Output From Last Stage Buffered Inputs CTyLp=ic1a5l pfMF,ATXA==5205MoHCz at VCC = 5V, Fanout (Over Temperature Range) - Standard Outputs 10 LSTTL Loads - Bus Driver Outputs . Wide O

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