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CD54HC195 4-Bit Parallel Access Register

CD54HC195 Description

Data sheet acquired from Harris Semiconductor SCHS165E September 1997 - Revised October 2003 CD54HC195, CD74HC195 High-Speed CMOS Logic 4-Bit Paralle.
Asynchronous Master Reset. J, K, (D) Inputs to First Stage. Fully Synchronous Serial or Parallel Data Transfer.

CD54HC195 Applications

* It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The two modes of operation, shift right (Q0-Q1) and parallel load, are controlled by the state of the Parallel Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J and K inpu

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4-Bit Parallel Access Register Texas Instruments
Texas Instruments CD54HC195-like datasheet