* Description
* Asynchronous Master Reset
* J, K, (D) Inputs to First Stage
* Fully Synchronous Serial or Parallel Data Transfer
* Shift Right and Parallel Load Capability
* Complementary Output From Last Stage
* Buffered Inputs
* CTyLp=ic1a5l
CD54HC195
0.96 MB
4-bit parallel access register.
Data sheet acquired from Harris Semiconductor SCHS165E
September 1997 - Revised October 2003
CD54HC195, CD74HC195
High-Speed CMOS Logic 4-Bit Paralle.
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