* Description
* Digital Design Avoids Analog Compensation Errors
* Easily Cascadable for Higher Order Loops
* Useful Frequency Range - K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ) - I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz
CD54HC297 Datasheet (273.75 KB)
CD54HC297
273.75 KB
Digital phase-locked loop.
Data sheet acquired from Harris Semiconductor SCHS177B
November 1997 - Revised May 2003
CD54HC297, CD74HC297, CD74HCT297
High-Speed CMOS Logic Digita.
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