* Description
* Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times
* Asynchronous Set and Reset
* Complementary Outputs
* Buffered Inputs
* TTAyp=ic2a5lofCMAX = 60MHz at VCC = 5V, CL = 15pF,
* Fanout (Over Te
CD54HCT112 Datasheet (806.08 KB)
CD54HCT112
806.08 KB
Dual j-k flip-flop.
Data sheet acquired from Harris Semiconductor SCHS141H
March 1998 - Revised October 2003
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
Dual J-K Flip-F.
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