Description
Data sheet acquired from Harris Semiconductor SCHS185C September 1997 - Revised October 2003 CD74HC390, CD54HCT390, CD74HCT390 High-Speed CMOS Logic .
Two BCD Decade or Bi-Quinary Counters.
One Package Can Be Configured to Divide-by-2, 4, 5,10, 20, 25, 50 or 100.
Two Maste.
Applications
* of divide-by-2, 4. 5, 10, 20, 25, 50 or 100. Each section is triggered by the High-to-Low transition of the input pulses (nCP0 and nCP1). For BCD decade operation, the nQ0 output is connected to the nCP1 input of the divide-by-5 section. For bi-quinary decade operation, the nO3 output is connected t
