* Description
* Fully Static Operation
* Buffered Inputs
* Common Reset
* Negative Edge Clocking
* Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
CD54HCT4024 Datasheet (1.02 MB)
CD54HCT4024
1.02 MB
7-stage binary ripple counter.
Data sheet acquired from Harris Semiconductor SCHS202C
November 1997 - Revised October 2003
CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024
High-Spe.
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