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CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer

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Description

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CDCLVD1204 SCAS898B * MAY 2010 * REVISED OCT.
The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through O.

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Features

* 1 2:4 Differential Buffer
* Low Additive Jitter:

Applications

* Telecommunications and Networking
* Medical Imaging
* Test and Measurement Equipment
* Wireless Communications

CDCLVD1204 Distributors

📁 Related Datasheet

CDCLD080 CDCLD100 CDCLD120 CDCLD200 CDCLD400 CDCLD500

📌 All Tags

CDCLVD1204 Low Additive Jitter LVDS Buffer Texas Instruments
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