SN54LV20A Datasheet - Texas Instruments

SN54LV20A DUAL 4-INPUT POSITIVE NAND GATE

ordering information These dual 4-input positive-NAND gates are designed for 2-V to 5.5-V VCC operation. The ’LV20A devices perform the Boolean function Y = A * B * C * D or Y = A + B + C + D in positive logic. These devices are fully specified for partial-power-down applicat.

SN54LV20A, SN74LV20A DUAL 4ĆINPUT POSITIVEĆNAND GATE D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C D Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C D Ioff Supports Partial-Power-Down Mode Operation D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged.

SN54LV20A Datasheet (966.86 KB)