SN65LVDS116
FEATURES
- One Receiver and Sixteen Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
- Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz
- Enabling Logic Allows Separate Control of Each Bank of Four Channels or 2-Bit Selection of Any One of the Four Banks
- Low-Voltage Differential Signaling With Typical Output Voltage of 350 m V and a 100-Ω Load
- Electrically patible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL, or HSTL Outputs With External Termination Networks
- Propagation Delay Times < 4.7 ns
- Output Skew Is < 300 ps and Part-to-Part Skew < 1.5 ns
- Total Power Dissipation Typically 470 m W With All Ports Enabled and at 200 MHz
- Driver Outputs or Receiver Input Is High Impedance When Disabled or With VCC < 1.5 V
- Bus-Pin ESD Protection Exceeds 12 k V
- Packaged in Thin Shrink Small-Outline Package With 20-Mil Terminal Pitch
DESCRIPTION
The SN65LVDS116 is one differential line receiver connected to sixteen...
