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SN65LVDS388 Datasheet - Texas Instruments

SN65LVDS388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

The ‘LVDS388 and ‘LVDT388 (T designates integrated termination) are eight differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA.

SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS D Eight Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard D Integrated 110-Ω Line Termination Resistors on LVDT Products D Designed for Signaling Rates† Up To 630 Mbps D SN65 Version’s Bus-Terminal ESD Exceeds 15 kV D Operates From a Single 3.3-V Supply D Propagation Delay Time of 2.6 ns (Typ) D Output Skew 100 ps (Typ) Part-To-Part Skew Is Less Than 1 ns D LVTTL Levels Are 5-V To.

SN65LVDS388 Datasheet (320.60 KB)