* 1 4:27 LVDS-to-CMOS Deserializer
* Pixel Clock Range of 4 MHz to 54 MHz, for Resolutions of 160 × 120 to 1024 × 600
* Special 2:27 Mode With 14x Sampling Allows Using Just Two Data Lanes
* Very Low EMI With 3-Way Selectable CMOS Slew Rate
* Supports Single 3.
SN65LVDS822 Datasheet (2.43 MB)
SN65LVDS822
2.43 MB
Lvds receiver.
Product Folder
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SN65LVDS822
SLLSEE8B
* SEPTEMBER 2013
* REVI.
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