SN65LVDS822 - LVDS Receiver

Texas Instruments

Datasheet Details

The SN65LVDS822 is an advanced FlatLink™ lowvoltage differential signal (LVDS) receiver designed on a modern CMOS process.

1 4:27 LVDS-to-CMOS Deserializer.
Pixel Clock Range of 4 MHz to 54 MHz, for Resolutions of 160 × 120 to 1024 × 600.
Special 2:27 Mode With 14x Sampling Allows Using Just Two Data Lanes.
Very Low EMI With 3-Way Selectable CMOS Slew Rate.
Supports Single 3.3-V Power Supply; VDDIO Allows 1.8 V to 3.3 V for Flexible Panel Support.
Clock Output is Rising or Falling Edge.
Bus-Swap Feature for Flexible PCB Layout.
Integrated Switch.

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Published: Aug 6, 2024 |