* Operation of 4.5V to 5.5V VCC
* Inputs accept voltages to 5.5V
* Max tpd of 8.5ns at 5V
* Inputs are TTL-voltage compatible
* 3-state inverted outputs drive bus lines directly
* Flow-through architecture to optimize PCB layout
* Full parallel
SN74ACT564 Datasheet (1.34 MB)
SN74ACT564
1.34 MB
Octal d-type edge-triggered flip-flops.
SN74ACT564
SCAS549D
* NOVEMBER 1995
* REVISED FEBRUARY 2024
SN74ACT564 Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputs
1 .
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