SN74ALS112A Datasheet - Texas Instruments

SN74ALS112A Dual J-K Negative-Edge-Triggered Flip-Flop

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requir.

SN54ALS112A, SN74ALS112A DUAL JĆK NEGATIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET SDAS199A APRIL 1982 REVISED DECEMBER 1994 Fully Buffered to Offer Maximum Isolation From External Disturbance Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs TYPE ′ALS112A TYPICAL MAXIMUM CLOCK FREQUENCY (MHz) 50 TYPICAL POWER DISSIPATION PER FLIP-FLOP (mW) 6 SN54ALS112.

SN74ALS112A Datasheet (1.00 MB)