SN74AS74A, SN74ALS74A Datasheet - Texas Instruments

SN74AS74A Dual Positive-Edge-Triggered D-Type Flip-Flops

These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requ.

SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SDAS143C APRIL 1982 REVISED AUGUST 1995 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs TYPE ′ALS74A ′AS74A TYPICAL MAXIMUM CLOCK FREQUENCY (CL = 50 pF) (MHz) 50 134 TYPICAL POWER DISSIPATION PER FLIP-FLOP (mW) 6 26 SN54ALS74A, SN54AS74A . . . J PACKAGE SN7.

SN74ALS74A-etcTI.pdf