TMS320C5534 - Ultra-Low Power DSP
52 1.4.3 Configuration 54 1.4.4 Clock Generator Registers 58 1.5 Power Management 62 1.5.1 Overview 62 1.5.2 Power Domains 62 1.5.3 Clock Management 63 1.5.4 Static Power Management 75 1.5.5 Power Considerations 79 1.5.6 Power Configurations 84 1.6 Interrupts 88 1.6.1 IFR and IER Registers 89
TMS320C5545/35/34/33/32 Ultra-Low Power DSP Technical Reference Manual Literature Number: SPRUH87H August 2011 Revised April 2016 Contents Preface 33 Revision History 34 1 System Control 35 1.1 Introduction 36 1.1.1 Block Diagram 37 1.1.2 Device Differences 39 1.1.3 CPU Core 40 1.1.4 FFT Hardware Accelerator (TMS320C5545/35 Only) 40 1.1.5 Power Management 42 1.1.6 Peripherals 42 1.2 System Memory 42 1.2.1 Program/Data Memory Map 43 1.2.2 I/O Memory Map 48 1.3 Device Clocking
