Description
TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880P * DECEMBE.
Features
* Dual-core architecture
* Two TMS320C28x 32-bit CPUs
* 200MHz
* IEEE 754 single-precision Floating-Point Unit
(FPU)
* Trigonometric Math Unit (TMU)
* Viterbi/Complex Math Unit (VCU-II)
* Two programmable Control Law Accelerators (CLAs)
Applications
* intellectual property matters and other important disclaimers. PRODUCTION DATA. TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D
SPRS880P
* DECEMBER 2013
* REVISED FEBRUARY 2024
www. ti. com
* Functi