TMS417800A Datasheet - Texas Instruments

TMS417800A DYNAMIC RANDOM-ACCESS MEMORIES

This data sheet is applicable to all TMS417800As symbolized by Revision “E” and subsequent revisions as described in the device symbolization section. D Organization . . . 2 097152 × 8 D Single 5-V Power Supply (± 10% Tolerance) D 2 048-Cycle Refresh in 32 ms D Performance Ranges: ACCESS ACCESS ACCESS READ OR TIME tRAC MAX TIME tCAC MAX TIME tAA MAX EDO CYCLE MIN ’417800A-50 ’417800A-60 50 ns 13 ns 60 ns 15 ns 25 ns 30 ns 20 ns 25 ns ’417800A-70 70 ns 18 ns 35 ns 30 ns D Enhanced Pa.

TMS417800A Features

* maximum RAS access times of 50-, 60-, and 70 ns. All addresses and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility. The TMS417800A is offered in a 28-lead plastic surface-mount SOJ package (DZ suffix). This package is designed fo

TMS417800A-etcTI.pdf