74ALVCH162827DGG Description
74ALVCH162827 20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state Rev.2 * 19 January 2018 Product data she.
The 74ALVCH162827 20-bit buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity.
74ALVCH162827DGG Features
* CMOS low power consumption
* MultiByte flow-through standard pin-out architecture
* Low inductance multiple VCC and GND pins for minimum noise and ground bounce
* Direct interface with TTL levels (2.7 V to 3.6 V)
* Bus hold on data inputs
* Current
74ALVCH162827DGG Applications
* such as memory address drivers, clock drivers and bus receivers/transmitters. To ensure the high impedance state during power up or power down, nOEn should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of
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