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74LV595D - 8-bit serial-in/serial-out or parallel-out shift register

This page provides the datasheet information for the 74LV595D, a member of the 74LV595 8-bit serial-in/serial-out or parallel-out shift register family.

Datasheet Summary

Description

The 74LV595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs.

Both the shift and storage register have separate clocks.

Features

  • Wide supply voltage range from 1.0 V to 3.6 V.
  • CMOS low power dissipation.
  • Direct interface with TTL levels.
  • Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C.
  • Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C.
  • Has a shift register with direct clear.
  • Output capability:.
  • Parallel outputs; bus driver.
  • Serial output; standard.
  • Latch-up performance exc.

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Datasheet preview – 74LV595D

Datasheet Details

Part number 74LV595D
Manufacturer nexperia
File Size 274.53 KB
Description 8-bit serial-in/serial-out or parallel-out shift register
Datasheet download datasheet 74LV595D Datasheet
Additional preview pages of the 74LV595D datasheet.

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Full PDF Text Transcription

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74LV595 8-bit serial-in/serial-out or parallel-out shift register; 3-state Rev. 5 — 29 September 2021 Product data sheet 1. General description The 74LV595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.
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