TP07 Description
The TP07 has very low input offset voltage (100μV maximum) that is obtained by trimming at the wafer stage. The low offset voltages generally eliminate any need for external nulling.
TP07 Key Features
- Low Offset Voltage: 100μV Maximum
- Low Drift: ±0.9μV/°C
- High EMIRR: 84dB at 900MHz
- Low Noise: 19 nV/√Hz(f= 1kHz)
- Wide Input Voltage Range: 0 to ±14V
- Wide Supply Range: ±1.35V to ±18V
- Low Input Bias Current: 40pA Typical
- Below-Ground (V-) Input Capability to -0.3V
- Rail-to-Rail Output Voltage Range
- Unit Gain Stable