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ADEBC2808 - PC-133 SDRAM Unbuffered SO-DIMM

This page provides the datasheet information for the ADEBC2808, a member of the ADEBC2808_A PC-133 SDRAM Unbuffered SO-DIMM family.

Description

The ADEBC2808 is 32Mx64 bits Synchronous DRAM Modules, The modules are composed of eight 16Mx16 bits CMOS Synchronous DRAMs in TSOP-II 400mil 54pin package and one 2Kbit EEPROM in 8pin TSSOP(TSOP) package on a 144pin glass

epoxy printed circuit board.

Features

  • PC-133 support.
  • Auto refresh and self refresh.
  • 8192 refresh cycles / 64ms.
  • Single 3.3±0.3V power supply.
  • All device pins are compatible with LVTTL interface.
  • Data mask function by DQM.
  • Serial Presence Detect with EEPROM.
  • Module bank : two physical bank.
  • PCB : BSS960,Height (31.75mm),double sided component, Six layers Ordering Information. Part No. ADEBC2808 Frequency 133Mhz Bank 4 Banks Ref. 8K Package TSOP II Pin Assignm.

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Datasheet preview – ADEBC2808

Datasheet Details

Part number ADEBC2808
Manufacturer A-Data Technology
File Size 681.77 KB
Description PC-133 SDRAM Unbuffered SO-DIMM
Datasheet download datasheet ADEBC2808 Datasheet
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Full PDF Text Transcription

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A-Data www.DataSheet4U.com ADEBC2808 PC-133 SDRAM Unbuffered SO-DIMM 32Mx64bits SDRAM DIMM based on 16Mx16, 4Bank, 8K Refresh, 3.3V SDRAM General Description The ADEBC2808 is 32Mx64 bits Synchronous DRAM Modules, The modules are composed of eight 16Mx16 bits CMOS Synchronous DRAMs in TSOP-II 400mil 54pin package and one 2Kbit EEPROM in 8pin TSSOP(TSOP) package on a 144pin glass–epoxy printed circuit board. The A-Data is a Dual In-line Memory Module and is intended for mounting onto 144-pins edge connector sockets. Fully synchronous operation referenced to the positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock. The data paths are internally pipelined to achieve very high bandwidth.
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