VDS7608A4A - Synchronous DRAM (4M x 8 Bit x 4 Banks)

This page provides the datasheet information for the VDS7608A4A, a member of the VDS7608A4A_A Synchronous DRAM (4M x 8 Bit x 4 Banks) family.

Datasheet Summary

Description

The VDS7608A4A are four-bank Synchronous DRAMs organized as 4,194,304 words x 8 bits x 4 banks.

Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Features

JEDEC standard LVTTL 3.3V power supply.
MRS Cycle with address key programs -CAS Latency (2 & 3) -Burst Length (1,2,3,8,& full page) -Burst Type (sequential & Interleave).
4 banks operation.
All inputs are sampled at the positive edge of the system clock.
Burst Read single write operation.
Auto & Self refresh.
4096 refresh cycle.
DQM for masking.
Package:54-pins 400 mil TSOP-Type II Ordering Information. Part No. VDS7608A.

A-Data Technology

📥 Download Datasheet

Datasheet Details

Part number	VDS7608A4A
Manufacturer	A-Data Technology
File Size	208.88 KB
Description	Synchronous DRAM (4M x 8 Bit x 4 Banks)
Datasheet	VDS7608A4A Datasheet
Additional preview pages of the VDS7608A4A datasheet.

📁 Similar Datasheet

VDSGLD38.88 - Voltage Controlled Crystal Oscillator (ETC)
VDSL6100I - Integrated LR EoVDSL Modem-on-Chip (Infineon Technologies)

Other Datasheets by A-Data Technology

VDS7616A4A - Synchronous DRAM
VDS7616A4A-55 - Synchronous DRAM
VDS7616A4A-6 - Synchronous DRAM
VDS7616A4A-7 - Synchronous DRAM
VDS4616A4A - Synchronous DRAM
VDS6608A4A - Synchronous DRAM
VDS6616A4A - Synchronous DRAM
VDS6632A4A - Synchronous DRAM

Full PDF Text Transcription

Click to expand full text

V-Data Synchronous DRAM VDS7608A4A 4M x 8 Bit x 4 Banks General Description The VDS7608A4A are four-bank Synchronous DRAMs organized as 4,194,304 words x 8 bits x 4 banks. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features •JEDEC standard LVTTL 3.

Published: Apr 16, 2005 |