VDS7616A4A-6 Datasheet | A-Data Technology

Description The VDS7616A4A are four-bank Synchronous DRAMs organized as 2,097152 words x 16 bits x 4 banks. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features - JEDEC standard LVTTL 3.3V power supply - MRS Cycle with address key programs -CAS Latency (2 & 3) -Burst Length (1,2,4,8,& full page) -Burst Type (sequential & Interleave) - 4 banks operation - All inputs are sampled at the positive edge of the system clock - Burst Read single write operation - Auto & Self refresh - 4096 refresh cycle - DQM for masking - Package:54-pins 400 mil TSOP-Type II Ordering Information. Part No. Frequency Interface Package VDS7616A4A-55 183Mhz LVTTL 400mil 54pin TSOPII 166Mhz LVTTL 400mil 54pin TSOPII VDS7616A4A-7 Pin Assignment 143Mhz LVTTL 400mil 54pin TSOPII DQ0 VDDQ DQ1 DQ2 VSSQ...