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HMS30C7202 - Highly-integrated MPU

General Description

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Change The First Draft PMU Freq.

Key Features

  • 32-bit ARM7TDMI RISC static CMOS CPU core : Running up to 70 MHz 8Kbytes combined instruction/data cache Memory management unit Supports Little Endian operating system 2Kbytes SRAM for internal buffer memory On-chip peripherals with individual power-down: - Multi-channel DMA - 4 Timer Channels with Watch Dog Timer - Intelligent Interrupt Controller - Memory controller for ROM, Flash, SRAM, SDRAM HMS30C7202 - Powermanagementunit - LCD Controller for mono/color STN and TFT LCD - Real-time clock (3.

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Datasheet Details

Part number HMS30C7202
Manufacturer ABOV
File Size 7.46 MB
Description Highly-integrated MPU
Datasheet download datasheet HMS30C7202 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HMS30C7202 Highly-integrated MPU (ARM Based 32-Bit Microprocessor) Datasheet Version 1.9 ABOV Semiconductor Ltd. HMS30C7202 HMS30C7202 © 2006 ABOV Semiconductor Ltd. All Rights Reserved. - ii - Version 1.9 HMS30C7202 Copyright. 2006 ABOV Semiconductor Ltd. ALL RIGHTS RESERVED. No part of this publication may be copied in any form, by photocopy, microfilm, retrieval system, or by any other means now known or hereafter invented without the prior written permission of ABOV Semiconductor Inc. HMS30C7202 ABOV Semiconductor Inc. 7th floor, 1007-3, Daechi-dong, Gangnam-gu, Seoul, 135-738, Republic of Korea (South Korea) Homepage: www.abov.co.kr H.Q. of ABOV Semiconductor Ltd.