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AK5322048BW - 2097152 Word by 32 Bit CMOS Dynamic Random Access Memory

Description

The Accutek AK5322048BW high density memory module is a CMOS dynamic RAM organized in 2048K x 32 bit words.

The module consists of four standard 1 Meg x 16 bits DRAMs in plastic SOJ packages.

Features

  • 2,097,152 x 32 bit organization.
  • 72 pad Single In-Line Module.
  • CAS-before-RAS, RAS-only or hidden refresh.
  • Operating free air temperature 0oC to 70oC.
  • Single 5 Volt Power Supply.
  • 1024 Refresh Cycles, 16 mSEC.
  • Available in Fast Page Mode or EDO.
  • Power: 3.96 Watt Max Active (50nS) 3.52 Watt Max Active (60 nS) 3.08 Watt Max Active (70 nS) 44 mW Max Standby.
  • Downward compatible with AK5321024W, AK532512W and AK532256W.
  • Upward compatible with AK5324.

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Datasheet Details

Part number AK5322048BW
Manufacturer ACCUTEK
File Size 148.71 KB
Description 2097152 Word by 32 Bit CMOS Dynamic Random Access Memory
Datasheet download datasheet AK5322048BW Datasheet

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Other Datasheets by ACCUTEK

Part Number Description
AK5322048 2097152 Word by 32 Bit CMOS Dynamic Random Access Memory
AK5322048N 2097152 Word by 32 Bit CMOS Dynamic Random Access Memory
AK532256AW 262144 Word by 32 Bit CMOS Dynamic Random Access Memory
AK532256W 262144 Word by 32 Bit CMOS Dynamic Random Access Memory
AK5321024N 1048576 Word by 32 Bit CMOS Dynamic Random Access Memory

Full PDF Text Transcription

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MICROCIRCUIT CORPORATION DESCRIPTION The Accutek AK5322048BW high density memory module is a CMOS dynamic RAM organized in 2048K x 32 bit words. The module consists of four standard 1 Meg x 16 bits DRAMs in plastic SOJ packages. The assembly has two DRAMs mounted on each side of a printed circuit board in a 72 pad leadless SIM configuration. This configuration allows socket-mounting of large quantities of memory in applications where high density and ease of inserting additional memory are important. The operation of the AK5322048BW is identical to sixteen 1 Meg x 4 DRAMs. There are four CAS lines and two RAS lines. On each bank of 1M x 32, independent byte control is accomplished by four CAS lines. Each seperate CAS line controls one byte of the 1 Meg x 16 DRAM.
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