ACCUTEK AK591024AS
the AK591024 is identical to two 1 Meg x 4 plus one 1 Meg x 1 DRAMs. For the lower eight bits, the data input is tied to data output and brought out separately for each 1 Meg x 4 device, with common RAS, CAS and WE control. The OE pins are tied to Vss which dictates the use of early-write cycles to prevent contention of D and Q.DESCRIPTION
The Accutek AK591024 high density memory modules is a random access memory organized in 1 Meg x 9 bit words. The assembly consists of two 1 Meg x 4 and one 1 Meg x 1 DRAMs in surface mount packages mounted on the front side of a printed circuit board. The module can be configured as a leadless 30 pad SIM or a leaded 30 pin SIP. This packaging approach provides a better than 6 to 1 density increase over standard DIP packaging. The operation of Since the Write-Enable (WE) signal must always go low before CAS in a write cycle, Read-Write and Read-Modify-Write operation is not possible. For the ninth bit, the data input (D9) and data output (Q9) pins are brought out separately and controlled by a separate PCAS for that bit. Bit nine is generally used for parity. ACCUTEK AK591024AS / AK591024AG 1,048,576 Word X 9 bit, CMOS Dynamic Random Access Memory Front View 30-Pin SIM + 1 + 30 30-Pin SIP + 1 +FEATURES
● 1,048,576 x 9 bit organization● Optional 30 Pad SIM (Single In-Line M...