ACCUTEK AK59256AG
the AK59256A is identical to two 256K x 4 DRAMs plus one 256K x 1 DRAM. For the lower eight bits data input is tied to data output and brought out separately for each 256K x 4 device, with common RAS, CAS and WE control. The OE pins are tied to Vss which dictates the use of early-write cycles to prevent contention of D and Q.DESCRIPTION
The Accutek AK59256A high density memory modules is a random access memory organized in 256K x 9 bit words. The assembly consists of two 256K x 4 and one 256K x 1 DRAMs in surface mount packages mounted to the front side of a printed circuit board. The module can be configured as a leadless 30 pad SIM or a leaded 30 pin SIP. This packaging approach provides a better than 6 to 1 density increase over standard DIP packaging. The operation of Since the Write-Enable (WE) signal must always go low before CAS in a write cycle, Read-Write and Read-Modify-Write operation is not possible. For the ninth bit, the data input (D9) and data output (Q9) pins are brought out separately and controlled by a separate PCAS for that bit. Bit nine is generally used for parity. ACCUTEK AK59256AS / AK59256AG 262,144 Word by 9 bit, CMOS Dynamic Random Access Memory Front View 30-Pin SIM + 1 + 30 30-Pin SIP + 1 +FEATURES
● 262,144 x 9 bit organization● Optional 30 Pad SIM (Single In-Line Module) o...