GENERAL DESCRIPTION
Main FEATURES
System Block Diagram System DESCRIPTION
Functional DESCRIPTION
Interface DESCRIPTION
Register DESCRIPTION
Pin DESCRIPTION
Timing DESCRIPTION
ELECTRICAL SPECIFICATIONS
Packaging Appendix Address Resolution Logic (The built-in ARL) 3 3 3 4 4 10 16 27 32 38 39 A1 40 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. 2 INTRODUCTORY Section Page Data Sheet: ACD82124 1. GENERAL DESCRIPTION
The device includes 24 independent 10/100 MACs. Speed can be automatically configured through the MDIO port. Each port can operate at either 10Mbps or 100Mbps. The core logic of the ACD82124, implemented with patent pending BASIQ (Bandwidth Assured Switching with Intelligent Queuing) technology, can simultaneously process 24 asynchronous 10/100Mbps port traffic. The Queue Manager inside the ACD82124 provides the capability of routing traffic with the same order of sequence, without any packet loss. A complete 24 port 10/100 switch can be built with the use of the ACD82124, 10/100 PHY and ASRAM.
