ACD82124 Datasheet | ACD

Description Main Features System Block Diagram System Description Functional Description Interface Description Register Description Pin Description Timing Description Electrical Specifications Packaging Appendix Address Resolution Logic (The built-in ARL) 3 3 3 4 4 10 16 27 32 38 39 A1 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. INTRODUCTORY Section Page Data Sheet: ACD82124 1. GENERAL DESCRIPTION The ACD82124 is a single chip implementation of a 24 port 10/100 Ethernet switch system intended for IEEE 802.3 and 802.3u patible networks. The device includes 24 independent 10/100 MACs. Each MAC interfaces with an external PMD/PHY device through a standard MII interface. Speed can be automatically configured through the MDIO port. Each port can operate at either 10Mbps or 100Mbps. The core logic of the ACD82124, implemented with patent pending BASIQ (Bandwidth Assured Switching with Intelligent Queuing) technology, can simultaneously process 24 asynchronous 10/100Mbps port traffic. The Queue Manager inside the ACD82124 provides the capability of routing traffic with the same order of sequence, without any packet loss. A plete 24 port 10/100 switch can be built with the use of the ACD82124, 10/100 PHY and ASRAM. The MAC addresses can be expanded from the built-in 2K to 11K by the use of ACD’s external ARL chip (ACD80800 Address Resolution Logic). Advanced network management features can be supported with the use of ACD’s MIB (ACD80900 Management Information Base) chip. 2. FEATURES Data Sheet: ACD82124 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. - - - - - - - - - - - - - - - - - - 3. SYSTEM BLOCK DIAGRAM FIFO MAC-0 FIFO Buffer Buffer Lookup Engine (2K MAC Addr.) BIST Handler LED Controller PMD/ PHY-0 PMD/ PHY-1 FIFO MAC-1 FIFO Buffer Buffer Queue...