AHA AHA4702
The AHA4702 FEC decoder core is fully ENCODER/DECODER: compliant with section 5.3 of the Digital Video • DVB-S2 compliant Broadcast S2 (DVB-S2) standard. It is capable of • LDPC inner code with a BCH outer code 85 Mbit/sec user data rate with a 2/3 rate LDPC • 36 Msymb/s channel rate Code and 25 iterations in an FPGA. The core • Supported codes: 1/4 through 9/10 code rates supports all codes, frame sizes, and interleave schemes set forth in the DVB-S2 specification for broadcast, interactive, digital satellite news gathering, and professional services.| Part No. | AHA4702 |
|---|---|
| Datasheet | AHA4702 Download |
| Manufacturer | AHA |
| Description | DVB-S2 Compliant LDPC/BCH Forward Error Correction (FEC) Decoder Core |
| Buy | Stock & Price |
FEATURES
The core ryallows code and modulation changes on a block-by- block basis to fully support both Adaptive Coding and Modulation (ACM) and Variable Coding and aModulation (VCM). inThe AHA4702 FEC decoder core is comprised of a Low Density Parity Check (LDPC) inner code concatenated with a BCH outer code. It provides a limwide range of code rates from 1/4 to 9/10 and interleave depths from 1 (no interleaving) to 5 bits/symbol. The ACM/VCM support allows configuration changes of the FEC core on a block- reby-block basis while streaming without any data loss. In band signaling can control code and pmodulation changes for applications that use● Supported block sizes: 16K and 64K block sizes
● Packet Error Rate performance to 10E-7
● Auto Iterations to optimize code performance
● Full ACM and VCM compliance OTHERS
● Available as ASIC core upon request
● JTAG (available in ASIC version of the core)
● LLR demapper optionally available with FEC core.
● Available for both Altera and Xilinx FPGA platforms
● 155 Mbit/sec data rate in an ASIC EVALUATION TOOLS
● For free evaluation software, please contact AHA.
