Datasheet4U Logo Datasheet4U.com

AK8181F - 3.3V LVPECL 1:4 Clock Fanout Buffer

General Description

The AK8181F is a member of AKM’s LVDS clock fanout buffer family designed for telecom, networking and computer applications, requiring a range of clocks with high performance and low skew.

The AK8181F distributes 4 buffered clocks.

Key Features

  • Four differential 3.3V LVDS outputs Selectable differential PCLK0p/n or LVPECL clock inputs PCLK0p/n pair can accept the following differential input levels; LVDS, LVPECL, LVHSTL, SSTL, HCSL PCLK1p/n supports the following input types; LVPECL, CML, SSTL Clock output frequency up to 650MHz Translates any single-ended input signal to 3.3V LVDS levels with resistor bias on PCLK0n input Output skew : 30ps (maximum) Part-to-part skew : 600ps (maximum) Propagation delay : 2.5ns (maximum) Operating Tem.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
AK8181B 3.3V LVPECL 1:4 Clock Fanout Buffer Asahi Kasei Microsystems
AK8126 Spread Spectrum Clock Generator Asahi Kasei Microsystems
AK8133 Low Suprious Multiclock Generator Asahi Kasei Microsystems
AK80A AMPSS Power Modules Astec America
AK8406A AK8406A Asahi Kasei Microsystems

Other Datasheets by AKM (Asahi Kasei Microdevices)

Part Number Description
AK8181C 3.3V LVPECL 1:2 Clock Fanout Buffer
AK8181E 3.3V LVPECL 1:4 Clock Fanout Buffer
AK8181G 3.3V LVDS 1:4 Clock Fanout Buffer
AK8181H LVPECL 1:10 Clock Fanout Buffer
AK8185A Low - Jitter Clock Generator

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
AK8181F Preliminary 3.3V LVDS 1:4 Clock Fanout Buffer AK8181F Features Four differential 3.3V LVDS outputs Selectable differential PCLK0p/n or LVPECL clock inputs PCLK0p/n pair can accept the following differential input levels; LVDS, LVPECL, LVHSTL, SSTL, HCSL PCLK1p/n supports the following input types; LVPECL, CML, SSTL Clock output frequency up to 650MHz Translates any single-ended input signal to 3.3V LVDS levels with resistor bias on PCLK0n input Output skew : 30ps (maximum) Part-to-part skew : 600ps (maximum) Propagation delay : 2.