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AK8181H - LVPECL 1:10 Clock Fanout Buffer

General Description

The AK8181H is a member of AKM’s LVPECL clock fanout buffer family designed for telecom, networking and computer applications, requiring a range of clocks with high performance and low skew.

The AK8181H distributes 10 buffered clocks.

Key Features

  • Ten differential 2.5V, 3.3V LVPECL outputs Two Selectable differential inputs PCLKxp/n pairs can accept the following differential input levels; LVPECL, LVDS, LVHSTL, SSTL, HCSL Clock output frequency up to 700MHz Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on PCLKxn input Output skew : 30ps typical Part-to-part skew : 340ps maximum Propagation delay : (T. B. D)ns maximum Additive phase jitter(RMS) : 0.045ps (typical) Operating Temperature Range: -40 to +85℃ P.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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AK8181H 2.5V, 3.3V LVPECL 1:10 Preliminary Clock Fanout Buffer AK8181H Features Ten differential 2.5V, 3.3V LVPECL outputs Two Selectable differential inputs PCLKxp/n pairs can accept the following differential input levels; LVPECL, LVDS, LVHSTL, SSTL, HCSL Clock output frequency up to 700MHz Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on PCLKxn input Output skew : 30ps typical Part-to-part skew : 340ps maximum Propagation delay : (T.B.D)ns maximum Additive phase jitter(RMS) : 0.