S3056 Overview
The function of the S3056 clock recovery unit is to derive high speed timing signals for SONET/SDHbased equipment. The S3056 is implemented using AMCC’s proven Phase Locked Loop (PLL) technology. Figure 1 shows a typical network application.
S3056 Key Features
- SiGe BiCMOS technology
- plies with Bellcore and ITU-T specifications for jitter tolerance, jitter transfer and jitter generation
- On-chip high frequency PLL with internal loop filter for clock recovery
- Selectable reference frequencies 19.44 MHz or 155.52 MHz (or equivalent Fibre Channel/ Gigabit Ethernet frequencies)
- Lock detect-monitors frequency of ining data
- Low-jitter serial interface
- +3.3 V supply
- pact 48 pin TQFP TEP package
- Typical power 620 mW
