AMCC S4850
The S4850 is divided into two independent clock recovery modules. The S4850 receives an OC-48 scrambled NRZ signal and recovers the clock from the data. S4850 Dual OC-48 SONET/SDH CRU with FEC Rate Support Product Brief PB2006_v1.00_01/26/05 Overview S485 0 The dual S4850 supports clock recovery for the OC-48 (+ FEC) data rates.| Part No. | S4850 |
|---|---|
| Datasheet | S4850 Download |
| Manufacturer | AMCC |
| Description | Dual OC-48 SONET/SDH CRU |
| Buy | Stock & Price |
FEATURES
●● CMOS 0.13 micron technology Complies with Bellcore and ITU-T specifications for jitter tolerance, jitter transfer, and jitter generation On-chip high-frequency PLLs for clock generation and clock recovery Supports clock recovery for 2.488 Gbps (OC-48) with FEC Selectable reference clock source (155.52 MHz for SONET or equivalent for FEC) Directly compatible with 1.2 V CML I/O 1.2 V, 3.3 V, 2.5 V and 1.8 V supply Lock detect Signal detect input (SD[B:A]) Bypass Mode Individual channel power off capability Typical 400 mW 121 Plastic Ball Grid Array Package
DESCRIPTION
The function of the S4850 clock and data recovery unit is to derive high speed timing signals for SONET/SDHbased equipment. The chip outputs a differential bit clock and retimed data. Figure 1 shows a typical network application. The S4850 utilizes two on-chip PLLs which consist of a phase detector, a loop filter, and a voltage controlled oscillator (VCO). The phase detector compares the phase relationship between the VCO output and the serial data input.