S4850 Overview
The function of the S4850 clock and data recovery unit is to derive high speed timing signals for SONET/SDHbased equipment. The S4850 receives an OC-48 scrambled NRZ signal and recovers the clock from the data. The chip outputs a differential bit clock and retimed data. Figure 1 shows a typical network application. The S4850 utilizes two on-chip PLLs which consist of a phase detector, a loop filter, and a voltage controlled oscillator (VCO). The phase detector pares the phase relationship between the VCO output and the serial data input. A loop filter converts the phase detector output into a smooth DC voltage, and the DC voltage is input to the VCO whose frequency is varied by this voltage. The S4850 is packaged in a 121 Plastic Ball Grid Array (PBGA), offering designers a small package outline. • • • • • • • • • • •