AM486DE2 Datasheet | AMD

Features - 3-V core with 5-V-tolerant I/O - Binary patible with all Am486® DX and Am486DX2 microprocessors - Wide range of support available through the AMD® Fusion E86SM Program s IEEE 1149.1 JTAG Boundary-Scan patibility s Supports Environmental Protection Agency's Energy Star program - 3-V operation reduces power consumption up to 40% - Energy management capability provides an excellent base for energy-efficient design - Works with a variety of energy-efficient, powermanaged devices .. s 208-Lead SQFP or 168-Pin PGA Package GENERAL DESCRIPTION The Am486DE2 microprocessor is an addition to the AMD Am486 microprocessor family. The Am486DE2 enhances system performance by incorporating flexible clock control and enhanced SMM. The Am486DE2 CPU clock control feature permits the CPU to be stopped under controlled conditions, allowing reduced power consumption during system inactivity. The SMM function is implemented with an industry-standard, two-pin interface. w w w . t a d h s a t e e . u 4 m o c Publication ID 20037 Revision A Amendment /0 Issue Date April 1996 .. BLOCK DIAGRAM Power Plane Clock Interface 32-Bit Data Bus 32-Bit Data Bus 32-Bit Linear Address PCD, PWT VOLDET VCC, VSS Clock Generator CLK STPCLK Bus Interface Cache Unit 32 Address Drivers Write Buffers 4x32 Copyback Buffers 4x32 Writeback Buffers 4x32 Barrel Shifter Register File ALU 24 Segmentation Unit Descriptor Registers Limit and Attribute PLA Paging Unit 24 Translation Lookaside Buffer A31- A2 BE3- BE0 Physical Address Physical Address 8-Kbyte Cache Displacement Bus Micro-instruction Prefetcher 32 Code 32-Byte Stream Code Queue Data Bus Transceivers D31- D0 ADS, W/R, D/C, M/IO, PCD, PWT, RDY, LOCK, PLOCK, BOFF, A20M, BREQ, HOLD, HLDA, RESET, INTR, NMI, FERR, UP, IGNNE, SMI, SMIACT, SRESET BRDY, BLAST BS16,...