Datasheet4U Logo Datasheet4U.com

AM53C96 - High Performance SCSI Controller

Download the AM53C96 datasheet PDF. This datasheet also covers the AM53C94 variant, as both devices belong to the same high performance scsi controller family and are provided as variant models within a single manufacturer datasheet.

General Description

The High Performance SCSI Controller (HPSC) has a flexible three bus architecture.

The HPSC has a 16-bit DMA interface, an 8 bit host data interface and an 8-bit SCSI data interface.

The HPSC is designed to minimize host intervention by implementing common SCSI sequences in hardware.

Key Features

  • C/D TSEL I/O.
  • I/O + I/O SDC 1 SD 1.
  • SD 0 + SD 0 SDC 0 SD 0 AMD 75ALS170 ISEL ATN.
  • ATN + ATN SDC 2 SD 2.
  • SD 1 + SD 1.
  • SD 2 + SD 2.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AM53C94_AMD.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number AM53C96
Manufacturer AMD
File Size 353.40 KB
Description High Performance SCSI Controller
Datasheet download datasheet AM53C96 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
PRELIMINARY Am53C94/Am53C96 High Performance SCSI Controller DISTINCTIVE CHARACTERISTICS s s s s s s s s s Pin/function compatible with NCR53C94/53C96 AMD’s Patented GLITCH EATERTM Circuitry on REQ and ACK inputs 5 Mbytes per second synchronous SCSI transfer rate 20 Mbytes per second DMA transfer rate 16-bit DMA Interface plus 2 bits of parity Flexible three bus architecture Single ended SCSI bus supported by Am53C94 Single ended and differential SCSI bus supported by Am53C96 Selection of multiplexed or non-multiplexed address and data bus s s s s s s s s Advanced Micro Devices High current drivers (48 mA) for direct connection to the single ended SCSI bus Supports Disconnect and Reselect commands Supports burst mode DMA operation with a threshold of 8 Supports 3-byte-tagged queuing as