FEATURES
UPDATE The basic feature description for SUPERNET 3 is provided in the SUPERNET 2 data book. The enhanced features are as listed below: s This is a CMOS integration of the redesigned FORMAC Plus, an enhanced PLC, a 32-entry address filter (AF, which is based on a Content Addressable Memory, or CAM, core), and a CMOS PDX core for clock and data recovery. s A 32-entry, extensible and fully maskable AF allows additional individual and group addresses to be supported. s The physical data transmitter and receiver (PDX) circuits are also embedded on-chip using proprietary digital clock-recovery technology. s For the purposes of implementing copper PMD, the scrambler/descrambler functions are embedded within the chip. s The Buffer Memory interface has been modified to support slower SRAM’s (35 ns) without affecting backward compatibility with SUPERNET 2. s SUPERNET 3 supports the FDDI single attachment station (SAS) but is capable of supporting a dual attachment station (DAS) This document contains information on a product under development at Advanced Micro Devices, Inc.
AMD
