GENERAL DESCRIPTION
Only a single +5V power supply is required for normal operation. A DC power-down mode reduces power while retaining data with a supply voltage as● low as 1.5V. All interface signal levels are identical to TTL specifications, providing good noise immunity and simplified system design. All inputs are purely capacitive MOS loads. The outputs will drive two full TTL loads or more than eight low-power Schottky loads. Operational cycles are initiated when the Chip Enable clock goes HIGH. When the read or write is complete, Chip Enable goes LOW to preset the memory for the next cycle. Address and Chip Select signals are latc11ed on-chip to simplify system timing. Output data is also latched and is available until the next operating cycle. The WE signal is HIGH for all read operations and is LOW during the Chip Enable time to perform a write. Data In and Data Out signals share common I/O pins. BLOCK DIAGRAM CONNECTION DIAGRAM AO A1 A2 ROW 64 ADDRESS 6 VCC (+S.OV) A3 ADDRESS...
AMD
