Am9147 Datasheet | AMD

DESCRIPTION The Am9147 is a high performance, 4096-bit, static, read/write, random access memory. It is organized as 4096 words by one bit per word. All interface signal levels are identical to TTL specifications, providing good noise immunity and simplified system design. All inputs are purely capacitive MOS loads. The outputs will drive up to seven standard Schottky TTL loads or up to six standard TTL loads. Only a single +5 volt power supply is required. When deselected (CS ?: VIH), the Am9147 automatically ente-rs a power-down mode which reduces power dissipation by more than 85%. When selected, the chip powers up again with no access time penalty. Data In and Data Out use separate pins on the standard 18-pin package. Data Out is the Same polarity as Data In. Data Out is a 3-state signal allowing wired-or operation of several chips. Data In and Data Out may be connected together for operation in a mon data bus environment. f J BLOCK DIAGRAM CONNECTION DIAGRAM Top View Al ADDRESS A2 BUFFERS A3 A6 DECODERS A7 A4 ADDRESS BUFFERS A9 COLUMN DECODERS All CS WE VCCVSS-- STORAGE CELL MATRIX 64 x 64 SENSE/WRITE AMPLIFIERS 1/0 CONTROL AND BUFFER ADDRESS 0 ADDRESS 1 ADDRESS 2 ADDRESS 3 ADDRESS 4 ADDRESS 5 DATA OUT WRITE ENABLE (GND) VSS VCC (+SV) ADDRESS 6 ADDRESS 7 ADDRESS S ADDRESS 9 ADDRESS 10 ADDRESS 11 DATA IN CHIP SELECT DATA DATA OUT IN MOS-267 Note: Pin 1 is marked for...