SB710 Description
Updated Figure 3-1, “SB710 Power Up/Down Sequence”: Corrected SLP_S5#/SLP_S3# timing diagram.
SB710 Key Features
- Updated Figure 12-1, “SB710 FCBGA Package Outline” with a picture of better quality
- Updated Table 9-5, “RTC X1 Clock AC Specifications”: Removed cycle-tocycle jitter requirement
- Updated Section 7.13, “SMBus Interface/GPOC”: Noted that SCL and SDA pins are OD when configured as SMBus pins
- Updated Table 9-5, “RTC X1 Clock AC Specifications”: Corrected unit for T62 to T65 to µS
- First release of the public version