DESCRIPTION
Logic Symbol Truth Table AA3x A BQ C A BQ C A B CQ L XX L XLXL XXL L HHHH HDL Syntax Verilog .................... AA3x inst_name (Q, A, B, C); VHDL...................... inst_name: AA3x port map (Q, A, B, C); Pin Loading Pin Name A B C AA31 1.0 1.0 1.0 Equivalent Loads AA32 AA34 1.0 2.1 1.0 2.1 1.0 2.1 AA36 3.1 3.1 3.1 Size And Power Characteristics Cell AA31 Equivalent Gates 2.0 Power Characteristicsa Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) TBD 3.7 AA32 AA34 AA36 3.0 6.0 8.0 TBD TBD TBD 5.1 9.9 12.6 a. See page 2-15 for power equation. 3-3 $$ [ $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process AA31 Number of Equivalent Loads From: Any Input To: Q tPLH tPHL Number of Equivalent Loads 1 0.36 0.25 1 4 0.48 0.37 8 AA32 From: Any Input To: Q tPL
AMI
