DESCRIPTION
Logic Symbol Truth Table A AN5x ABCDEQ B HHHXX L C Q XXXHHL D All other combinations H E Core Logic HDL Syntax Verilog .................... AN5x inst_name (Q, A, B, C, D, E); VHDL...................... inst_name: AN5x port map (Q, A, B, C, D, E); Pin Loading Pin Name A B C D E AN52 1.0 1.0 1.0 1.0 1.0 Equivalent Loads AN54 1.0 1.0 1.0 1.0 1.0 AN56 2.1 2.1 2.1 2.2 2.2 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) AN52 4.0 TBD 8.0 AN54 5.0 TBD 9.4 AN56 12.0 TBD 18.6 a. See page 2-15 for power equation. 3-15 $1 [ ® $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Number of Equivalent Loads 1 4 AN52 From: Any Input To: Q tPLH tPHL 0.4
AMI
